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 From:  Jim Thompson <jim at netgate dot com>
 To:  "James W. McKeand" <james at mckeand dot biz>
 Cc:  <m0n0wall at lists dot m0n0 dot ch>
 Subject:  Re: [m0n0wall] ECM-3624
 Date:  Fri, 14 Oct 2005 17:14:50 -1000
On Oct 14, 2005, at 2:54 PM, James W. McKeand wrote:

> Boris Rudoy wrote:
>
>> http://www.evalue-tech.com/news/Datasheet/ECM-3624.pdf
>>
>> looks like very good m0n0 solution
>>
>
> Everything looks good except the chipset used for the Ethernet.  
> Realtek
> has left a bad taste in many people's mouths... Search the list for
> realtek and try to find a positive response.

well, there are many Realtek Ethernet chipsets.    This board has two  
RTL8101Ls on it.

This page has a comparison of the RTL8129 and RTL8139 chipsets, from  
Donald Becker, someone who *really understands*
these things in a deep and meaningful way.
http://www.scyld.com/rtl8139.html

Here's the pull quote:

----
The RTL8129 series is a low-cost design, and thus should be  
considered a "connectivity solution" rather a performance-oriented  
product.

The RTL8139 series improves on the integration and feature set,  
adding advanced features such as 802.3x Flow Control and  
incorporating the transceiver onto a single chip. The data transfer  
engine remains the same, with much improved PCI burst performance in  
the B and C versions.

While the chip is a bus master, it's not a descriptor-based bus  
master. The receive side transfers packets into a single linear ring  
(compile-time selectable as 8KB, 16KB, 32KB or 64KB) in host memory.  
The driver immediately copies the packets from the ring to newly- 
allocated buffers ("skbuffs"). Most other Fast Ethernet designs use a  
descriptor-based architecture, which allows packets the chip to  
transfer directly into pre-allocated maximum-sized skbuffs. The  
driver then optionally copies only tiny packets into smaller-sized  
skbuffs.

On the transmit side four register sets hold the address and size of  
the packets to be transmitted. While this results in a rather small,  
fixed-size transmit queue, four entries is adequate for full  
performance in most environments.

The transmit performance loss comes from an initially undocumented  
(yes, that means it took many hours to find) word-alignment  
requirement of the current chip. Linux cache-aligns the IP header and  
following payload data when constructing a packet. When the 14 byte  
Ethernet header is prepended, the complete packet is 2-byte aligned,  
but not 4-byte aligned. The result is that all IP packets must be  
copied to an alignment buffer before being queued for transmit.

--------

here is the EEPRO100 page for comparison:  http://www.scyld.com/ 
eepro100.html

 From what I can tell, the rtl8101 is essentially an 8139D in a  
different package.  I have a quite similar board here with 4 rtl8139s  
on the PCI bus (soldered down, not pci cards), 1GHz VIA C3 CPU, and  
it happily pushes 100Mbps across a pair of ports bridged.

So, lets not be so quick to damn all that says "Realtek".